Method of forming a vertical memory device with a rectangular trench

ABSTRACT

A method of forming a vertical memory device with a rectangular trench. First, a substrate covered by a photoresist layer is provided. Next, the photoresist layer is defined by a mask to form a rectangular opening, wherein the mask has two rectangular transparent patterns arranged with a predetermined interval. Next, the substrate is etched using the defined photoresist layer as a mask to form a single rectangular trench and the photoresist layer is then removed. Finally, a trench capacitor and a vertical transistor are successively formed in the rectangular trench to finish the vertical memory device.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to lithography, and more particularly to a maskfor defining a rectangular trench and a method of forming a verticalmemory device with a rectangular trench by the mask to improve thethreshold voltage of transistor shift and increase the alignment processwindow.

2. Description of the Related Art

With the wide application of integrated circuits (ICs), several kinds ofsemiconductor devices with higher efficiency and lower cost are producedbased on different objectives. Dynamic random access memory (DRAM) issuch an important semiconductor device in the information andelectronics industry.

Most DRAMs presently have one transistor and one capacitor in one DRAMcell. Under increased integration, it is needed to shrink the size ofthe memory cell so as to manufacture the DRAM with higher memorycapacity and higher processing speed. A 3-D capacitor structure canreduce its occupation area in the semiconductor substrate, so the 3-Dcapacitor, such as a deep trench capacitor, is applied to thefabrication of DRAM of 64 megabits and above. Traditional DRAM with aplane transistor covers larger areas of the semiconductor substrate andcannot satisfy demands for high integration. Therefore, use of verticaltransistors which can save space is a current trend in fabrication ofmemory cells.

When the size of the trench capacitor and the vertical transistor areshrunk due to high integration, the alignment between the active areaand the deep trench becomes more important. Unfortunately, misalignmentis difficult to avoid in subsequent process. Moreover, the mask used forlithography is subjected to optical limitation, such as opticalproximity effect (OPE), increasing the difficulty of lithography. Forexample, when the light source passes through a desired trench pattern(rectangular trench pattern) on the mask onto the imaging layer, arounding trench pattern (oval trench pattern) is formed in the imaginglayer due to light diffraction.

FIG. 1 is a plane view of partial layout of the conventional mask fordefining a trench pattern. The mask 10 includes rectangular transparentregions 10 a to define deep trenches in a semiconductor substrate, suchas a silicon wafer.

FIG. 2 is a plane view of the alignment between the active area and thetrench in a semiconductor substrate. In FIG. 2, deep trenches aredefined by the mask 10 shown in FIG. 1. Here, in order to simplify thediagram, only one deep trench 12 is shown. As mentioned above, OPE makesthe trench 12 has an oval top view, but not a desired top view(rectangular). In addition, when the active area AA is formed, theactive area AA is shifted (as the active area AA′) due to misalignment.The misalignment between the active area AA′ and the rounding trench 12changes the overlapping area, shifting the threshold voltage of thevertical transistor (not shown) in the trench 12 and changing itselectrical properties. That is, the alignment process window isnarrowed. As a result, the yield of the memory devices is reduced.Moreover, the area of the oval trench 12 is smaller than the rectangularone, reducing the capacitor (not shown) below the vertical transistor inthe trench 12.

SUMMARY OF THE INVENTION

Accordingly, an object of the invention is to provide a mask fordefining a rectangular trench, wherein a single rectangular trench isdefined by at least two rectangular openings.

Another object of the invention is to provide a method of forming avertical memory device with a rectangular trench to increase the trencharea and the alignment process window for the active area and thetrench, thereby preventing the threshold voltage of the transistor ofthe vertical memory device shift and increasing the capacitance of thecapacitor of the vertical memory device.

Accordingly, a mask is provided for defining a rectangular trench. Themask includes a transparent substrate and a light-shielding layerdisposed thereon. The light-shielding layer has at least two rectangularopening patterns arranged with a predetermined interval to define asingle trench.

The transparent substrate can be quartz and the light-shielding layercan be chromium. Moreover, the predetermined interval is about 50-70 nm.Preferably, the predetermined interval is about 60 nm.

According to another object of the invention, a method of forming avertical memory device with a rectangular trench is also provided.First, a substrate covered by an imaging layer is provided. Next, theimaging layer is defined by a mask to form a rectangular opening,wherein the mask has at least two rectangular transparent patternsarranged with a predetermined interval. The substrate is etched usingthe defined imaging layer as a mask to form a single rectangular trench.Thereafter, the imaging layer is removed. Finally, a trench capacitorand a vertical transistor are successively formed in the rectangulartrench to finish the vertical memory device.

The imaging layer can be photoresist. The predetermined interval isabout 50-70 nm, preferably about 60 nm. Moreover, the rectangular trenchhas a length of about 700-800 nm and a width of about 500-600 nm.

DESCRIPTION OF THE DRAWINGS

For a better understanding of the present invention, reference is madeto a detailed description to be read in conjunction with theaccompanying drawings, in which:

FIG. 1 is a plane view of partial layout of the conventional mask fordefining a trench pattern;

FIG. 2 is a plane view of the alignment between the active area and thetrench in a semiconductor substrate;

FIG. 3 is a plane view of partial layout of the mask for defining atrench pattern according to the present invention;

FIGS. 4 a to 4 c are cross-sections showing a method of forming avertical memory device with a rectangular trench according to thepresent invention; and

FIG. 5 is a plane view of the alignment between the active area and thetrench in a semiconductor substrate according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

A preferred embodiment of the present invention is now described withreference to FIGS. 3, 4 a-4 c, and 5.

First, FIG. 3 is a plane view of partial layout of the mask for defininga trench pattern according to the present invention. The mask 20includes a transparent substrate 20 a and a light-shielding layer 20 bthereon. In this invention, the transparent substrate 20 a can be glassor quartz. The light-shielding layer 20 b can be chromium and has athickness of about 100-200 nm. In general, the light-shielding layer 20b is firstly formed on the transparent substrate 20 a by conventionaldeposition, such as sputtering. Next, the mask 20 for defining trenchesis completed after lithography and etching are successively performed onthe light-shielding layer 20 b to form a plurality of rectangularopening patterns 20 c therein.

Compared with the prior art, one trench pattern of the invention isdefined by at least two rectangular opening patterns 20 c arranged witha predetermined interval d. Here, the predetermined interval d is about50-70 nm, preferably about 60 nm. Since there is an interval d betweentwo rectangular opening patterns 20 c serving as an assistant pattern,the rounded edge of the trench pattern due to the optical proximityeffect (OPE) can be avoided. That is, it can prevent formation of anoval trench (a trench with an oval top profile). In addition, it isnoted that such single trench can be defined by more than tworectangular or square opening patterns where each opening pattern isarranged with a predetermined interval d.

FIGS. 4 a to 4 c are cross-sections showing a method of forming avertical memory device with a rectangular trench according to thepresent invention. First, in FIG. 4 a, a substrate 30, such as asemiconductor substrate is provided. A pad oxide layer and a pad nitridelayer are successively deposited on the substrate 30. Here, in order tosimplify the diagram, only a blank substrate 30 is shown. Next, animaging layer 22, such as photoresist, is coated on the substrate 30.Thereafter, lithography is performed on the imaging layer 22 using themask 20 shown in FIG. 3 to form a rectangular opening 31 therein.

Next, in FIG. 4 b, the substrate 30 is etched using the imaging layer 22having the rectangular opening 31 as a mask to form a deep rectangulartrench 33 therein. In the invention, the deep rectangular trench 33 hasa length of about 700-800 nm and a width of about 500-600 nm.

Finally, in FIG. 4 c, after the imaging layer 22 is removed, a trenchcapacitor 35 and a vertical transistor 41 are successively formed in thedeep rectangular trench 33 by conventional process to finish thevertical memory device, such as dynamic random access memory (DRAM). Inthis memory device, the trench capacitor 35 includes a bottom electrode32 formed in the substrate 30 near the bottom of the deep rectangulartrench 33, and a top electrode 34, such as polysilicon, formed in thelower trench 33. A capacitor dielectric layer 36 is also disposed in thelower trench 33 and around the top electrode 34.

Moreover, the vertical transistor 41 includes source/drain regions 40,46, a gate 44, and a gate dielectric layer 42. The source region 40 isformed in the active area AA′ of the substrate 30 near the top of thecapacitor 35 and the drain region 46 is formed near the top of thesubstrate 30. The gate 44, such as polysilicon, is formed in the uppertrench 33. The gate dielectric layer 42, such as thermal oxide, isdisposed between the source/drain regions 40, 46 and the gate 44.

An insulating layer 39, such as silicon oxide, is disposed between thegate 44 and top electrode 34 of capacitor 35 to serve as an insulator.Moreover, a collar oxide 38 is disposed over the capacitor dielectriclayer 36.

FIG. 5 is a plane view of the alignment between the active area AA′ andthe trench 33 in the substrate 30, and FIG. 4 c is also a cross-sectionalong I-I line in FIG. 5. Since the deep trench 33 is defined by opticalproximity correction using the mask 20 in FIG. 3, it has a desiredrectangular top view, rather than the oval top profile shown in theprior art. Accordingly, although the active area AA shifts due tomisalignment in the subsequent process, as the active area AA′ shown inFIG. 5, the overlapping area between the active AA′ and the deeprectangular trench 33 is not varied. That is, the threshold voltageshift of the vertical transistor can be prevented, thereby maintainingthe electrical properties of the memory device and expanding thealignment process window. Moreover, the rectangular trench 33 of theinvention has a larger area than the oval one in the prior art. That is,the capacitor formed in the rectangular trench 33 can has largercapacitance.

Therefore, according to the method of the invention, the yield can beincreased by increasing the alignment process window. Moreover,operation speed can be raised by increasing the capacitance of thetrench capacitor.

While the invention has been described by way of example and in terms ofthe preferred embodiments, it is to be understood that the invention isnot limited to the disclosed embodiments. To the contrary, it isintended to cover various modifications and similar arrangements (aswould be apparent to those skilled in the art). Therefore, the scope ofthe appended claims should be accorded the broadest interpretation so asto encompass all such modifications and similar arrangements.

1-5. (canceled)
 6. A method of forming a vertical memory device with arectangular trench, comprising the steps of: providing a substratecovered by an imaging layer; defining the imaging layer by a mask toform a rectangular opening, wherein the mask has at least tworectangular transparent patterns arranged with a predetermined interval;etching the substrate using the defined imaging layer as a mask to forma single rectangular trench; removing the imaging layer; and forming atrench capacitor and a vertical transistor in the rectangular trenchsuccessively to finish the vertical memory device.
 7. The method asclaimed in claim 6, wherein the substrate is a semiconductor substrate.8. The method as claimed in claim 6, wherein the imaging layer is aphotoresist substrate.
 9. The method as claimed in claim 6, wherein thepredetermined interval is about 50˜70 nm.
 10. The method as claimed inclaim 6, wherein the predetermined interval is about 60 nm.
 11. Themethod as claimed in claim 6, wherein the rectangular trench has alength of about 700˜800 nm.
 12. The method as claimed in claim 6,wherein the rectangular trench has a width of about 500-600 nm.
 13. Themethod as claimed in claim 6, wherein the vertical memory device is adynamic random access memory (DRAM) device.